Si/SiGe heterostructure semiconductor channel transistors produced directly in a bulk substrate are known. However, such transistors have the drawback of exhibiting SCEs (Short Channel Effects) and DIBL (Drain-Induced Barrier Lowering). More precisely, when the length of the transistor gate decreases, the potential at the center of the channel is greatly modified and therefore the threshold voltage of the transistor will be changed, since the potential barrier between the source and the drain is lowered. This is the SCE effect. To this is added the action of the drain potential, which will further lower the potential barrier, i.e. the DIBL effect.